1. Field of the Invention
The present invention relates to a simulator that performs a simulation on an operation of a semiconductor integrated circuit, and more particularly, to a fault simulator that performs a fault simulation by creating a signal pattern for use in a fault inspection of a semiconductor integrated circuit formed by a MOS transistor.
2. Description of the Related Art
A fault simulation model for use in this kind of the conventional fault simulator has been used for a fault simulation under a single degenerate mode. The single degenerate mode is in a simulating way of fixing each signal level in the whole input/output terminals as "H (high level)" or "L (low level)" in every block including one function, such as an AND circuit, an OR circuit, a flip flop circuit, or the like (hereinafter, referred to as a function block), in the assumption that only one fault exists in one circuit. When the signal level is fixed at "H" in the input/output terminals, it is called an "H fault". When it is fixed at "L", it is called an "L fault".
An operation of the fault simulation by the single degenerate mode will be described, by way of example, in a two input NAND circuit.
FIG. 6A is a symbolic view of a two input NAND circuit including two input, In1 and In2, and one output, Out1. FIG. 6B is a circuit view showing a constitution of the internal circuit of the NAND circuit illustrated in FIG. 6A. FIG. 6C is a truth table showing an operation in the case of applying the conventional fault model to the NAND circuit illustrated in FIGS. 6A and 6B.
The content of the truth table shown in FIG. 6C corresponds to the fault model for a simulation. With reference to FIG. 6C, when both signal level of the input In1 and In2 is "L", the signal level of the output Out1 is "H" at the normal time in the NAND circuit shown in FIG. 6A. Similarly, when the signal level of the input In1 is "L" and the signal level of the input In2 is "H", the signal level of the output Out1 is "H" at the normal time. When the signal level of the input In1 is "H" and the signal level of the input In2 is "L", the signal level of the output Out1 is "H" at the normal time. When both signal level of the input In1 and In2 is "H", the signal level of the output Out1 is "L" at the normal time.
When the input In1 is at the "L fault", it is shown in the truth table of FIG. 6C in the space of "In1=L" at the failure of the output Out1 that the signal level of the output Out1 is "H" when In1="H" and In2="H". This is different from the signal level "L" of the output Out1 at the normal time. Therefore, if there exists the case where In1="H" and In2="H" in a signal pattern created for a fault simulation, the "L fault" of the input In1 can be detected by the simulation with the use of this signal pattern.
For example, the signal pattern illustrated in the timing chart of FIG. 7 consists of three types of state. When the input In1 is at the "H fault", the signal level of the output Out1 is "L" in the first pattern. Accordingly, it is different from the signal level "H" of the output Out1 at the normal time, so that the "H fault" of the In1 can be detected in the first pattern. Similarly, when the input In1 is at the "H fault", it can be detected by the third pattern.
On the contrary, when the input In2 is at the "H fault", the signal level of the output Out1 is in accordance with the output Out1 at the normal time in the three patterns. Therefore, the "H fault" of the input In2 cannot be detected by the signal pattern shown in FIG. 7. When the output wave shape at a specific fault is in accordance with the output wave shape at the normal time as mentioned above, the fault simulator is arranged to inform a designer that the fault cannot be detected by the signal pattern. Then, the designer creates a signal pattern capable of detecting the "H fault" of the input In2 and adds it on to the signal pattern of FIG. 7.
The fault model for use in the above conventional fault simulator, however, is to be applied only to the "H fault" and "L fault" of the input/output in every function block. More specifically, an IC circuit formed by the MOS transistor, since the gate is insulated there, is characterized in that the electric potential of the gate is held if wiring connected with the gate becomes high impedance. This characteristic, however, is not reflected in the above conventional fault model. The simulation by the use of this fault model is unable to create a signal pattern for detecting a fault in the internal circuit of a function block. Therefore, the following problems have occurred.
FIG. 8 shows a selector circuit formed in the combination of three NAND circuits, Q1, Q2, Q3, and one inverter Q4, as a candidate for a simulation. When the simulation by the use of the conventional fault model is performed on the selector circuit illustrated, all the "H fault" and "L fault" in the selector circuit can be detected by the signal pattern indicated in the timing chart of FIG. 9.
Each internal circuit of the NAND circuits Q1, Q2, Q3 consists of two P-type transistors P1, P2 and two N-type transistors N1, N2 as illustrated in FIG. 6B. Consider the case where owing to a fault in the P-type transistor P1 of the internal circuit of the NAND circuit Q1, the transistor P1 still remains OFF even if a signal of the signal level "L" is supplied to the gate of the transistor P1 (such a fault of a transistor is, hereinafter, referred to as an OFF fault). The signal level of the output Z1 in the NAND circuit Q1 varies as indicated in the timing chart of FIG. 10. Specifically, the output terminal Z1 of the NAND circuit Q1 becomes high impedance at the point A. The electric potential in the output terminal Z1 gradually drops from "H", because the electric charge stored as the gate capacitance of the input terminal Z2 in the NAND circuit Q3 of the next stage and as the wiring capacitance between Z1-Z2 starts flowing. Therefore, the selector circuit of FIG. 8 will operate normally until the signal level of the output terminal Z1 in the NAND circuit Q1 drops below the VIHL level.
When a function block contains the above mentioned transistor fault, the state of a signal pattern varies in an IC inspection before the signal level of the output terminal drops below the VIHL level in the function block including the relevant transistor, because continuous period of each signal pattern is short. Thus, the IC inspection cannot find the fault of the circuit, permitting their shipment in the faulted state. In the destination, the continuous period of the identical signal pattern in a signal supplied to the circuit is not necessarily short. When a long signal pattern is supplied there, the electric potential of the output terminal in the function block including the fault of the transistor (the output terminal Z1 of the NAND circuit Q1 in the example of FIG. 8) gets below the VIHL level of the input terminal of the next stage owing to the discharge, which may produce a malfunction in the circuit.